1. Field
Various embodiments may relate generally to data communication buses. In particular, the present invention relates to the data to clock phase relationship in a source synchronous bus.
2. Background
Synchronous data communication buses transfer data at a fixed phase relationship to the rising and falling edges of the bus clock as the data and bus clock travel together in the same flight time on the bus from source to destination. (In a source synchronous data bus, the bus clock is generated and provided by a device, such as an integrated circuit chip, on the bus.) Conventionally, the phase relationship is the same in both (frequently referred to as xe2x80x9creadxe2x80x9d and xe2x80x9cwritexe2x80x9d) directions. Typically, a master device sends out data to one or more slave devices in a quadrature phase relationship (at a fixed 90 degree offset) with the bus clock and the slave device(s) sends data to the master device in quadrature phase relationship with the bus clock.
In the case of memory buses or input/output (I/O) data buses, the master device is frequently a memory controller or a storage device controller and the slave device(s) are frequently memory devices or storage devices. Thus, data sent from the master device to the slave device(s) is frequently described as being sent in the xe2x80x9cwritexe2x80x9d direction and the data sent from the slave device(s) to the master device is frequently described as being sent in the xe2x80x9creadxe2x80x9d direction. In the example of a Rambus memory subsystem, an clock chip at the end of the Rambus channel generates a ClockToMaster (CTM) clock signal, which passes through all the slave devices and goes into the master device. It then comes out of the master device as the ClockFromMaster (CFM) clock signal, again passes through all of the slave devices and is terminated at the end of the Rambus channel.
The slave device in conventional source synchronous buses relies upon a quadrature phase detector (QPD) in a delay locked loop (DLL) or phase locked loop (PLL) circuit to send out the data in quadrature phase relationship with the ClockToMaster bus clock. However, the poor performance and high power consumption of the QPD limits bus performance. These problems can become acute in buses with stringent clocking signal requirements, such as RDRAM buses (more commonly referred to as RDRAM channels). The distribution and spec allocation of the output centering of the RDRAM is larger than the master device. The major contributor of RDRAM to center error is the poor performance of the QPD.